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Chips
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Sierra II
Type 1 cryptographic engine - this page is a stub

Sierra is a highly-integrated embeddable cryptographic engine with NSA Type 1 cryptographic algorithms, implemented in a single chip, introduced around 2004 by Harris Corporation (now: L3Harris) in Rochester (NY,USA) [2]. Unlike the contemporary Citadel II chip – which is a non-Type 1 device – the Sierra II is used in a number of US military products, including the AN/PRC-152. Sierra II is the successor to the Sierra (or Sierra I) cryptographic engine that was released in 1998.


Products that use Sierra II
  • Harris RF-310M-HH, suite B compatible multiband handheld radio
  • AN/PRC-152, Harris Flacon III
Features
  • ≤ 300 Mbps
  • Legacy algorithm support
  • Low power consumption
  • Advanced programmability
  • Compliant with Joint Tactical Radio System (JTRS)
  • Compliant with Crypto Modernization Program (CMP)
  • 280-ball µBGA (16 x 16 mm), or 608-ball BGA (31 x 31 mm)
  • Temperature -40°C to +85°C
  • Voltage 1.8V DC (ASIC) or 3.3V (module)
  • Reprogrammable field software
  • Classification TS/SCI
Type 1 algorithms
  • WALBURN
  • GOODSPEED
  • ACCORDION
  • FIREFLY / Enhanced FIREFLY
  • JOSEKI Decrypt
  • High-assurance AES
Type 3 algorithms
  • DES,
  • Tripple DES (3DES)
  • AES
  • Digital Signature Standard (DSS)
  • Secure Hash Algorithm (SHA)
Type 4 algorithms
Key management
  • SARK / PARK (KY-57, KYV-5 and KG-84A/C OTAR)
  • DS-101 Key Fill
  • DS-102 Key Fill
  • SINGARS Mode 2/3 Fill
  • Benign Key / Benign Fill
Documentation
  1. Harris Sierra II, Programmable Cryptographic ASIC, product leaflet
    DS-296E. Harris Corporation, November 2015.
References
  1. L3Harris, Sierra II Programmable Cryptographic ASIC
    Retrieved November 2017.

  2. EE Times, NSA certifies Harris crypto module
    23 September 2004.
Further information
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© Crypto Museum. Created: Saturday 09 November 2019. Last changed: Monday, 13 May 2024 - 21:26 CET.
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